Ask HN: In modern CPUs how many μs to flip a NAND (or other) logic gate?

For logic gates there is a "setup" and "hold" time (logic level prior to gate flip, then hold that level) for an operation to be successfully performed and transmitted to the next stage. It should be in the chip's datasheet (if you wanted a precise and specific number). If you don't care about logic transmission and just want "flip" then look at the rise/fall time.

It depends on PVT. Process, Voltage, and Temperature. When chips are being synthesized all this is characterized for each logic cell like and gates, flip flops, etc. They are in .lib files that is sent into the synthesis tools. If you can get one of those files it will tell you all the numbers.

Can you be a bit more specific? You mean how long a NAND gates takes to "execute" a NAND operation? It's somewhere around 20 nano seconds.

I suspect it's actually better measured in femtosceonds, but either way is good.