When you look at the design of the hardware, the various busses and registers are of a fixed maximum size. For example, small micro-controllers might have 8 bit registers and data busses and 16 bit address busses. This in turn means that the arithmetic unit processes information at that chunk size. There have been attempts at variable word size architectures (especially in the early days) but the amount of circuitry required to marshall variable sized information in and out of fixed sized hardware resources became excessive. Similar concerns apply to arbitrary-precision FPUs. These architectural concerns then propagate to the cache designs, memory and and I/O channels.
Of course, these concerns only apply at the hardware level. There are virtual machines, e.g. Lisp systems, that implement variable sized operations.
