Devil always lurks in the details. That generic parameter is so sparsely defined in 1149.1 that I struggle to see any semblance of consistency between major reconfigurable device vendors, let alone vendors which don't actually integrate boundary-scan.

There's also a philosophical point: electrical schematics should document electrical intent. A BSDL-driven EDA approach which must consider arbitrary semiconductors would largely be constrained to simple I/O separation with a mechanical representation of physical package layout serving as fallback in the case of poor inference. This doesn't account for symbolic capability between PCADs either, e.g. multi-part symbols, variants, hidden pins, etc.

In summary, end result is pretty much a box with little to no functional intent conveyed, resulting in what I consider to be the worst type of schematic interpretation experience.