In practical designs, flip flop outputs are regularly used as clock inputs and asynchronous set/reset inputs. If you used this latch as the output latch in a flip flop, it would glitch on the falling edge of the flip flop clock.

I didn't go through the entire game, so its entirely possible that it would not affect this particular "design". But as its far more educational than practical, I think its still worth mentioning.

> Especially because the d-flipflops found in standard cell libraries are frequently implemented as what amounts to two muxes and some inverters.

I'm curious where you've seen that implementation because I've never seen anything like that. Most of what I've seen uses two tri-state inverter latches.