One of RISC-V's main goals is to be boring and extensible. Think if it as the control-plane core, or the EFI for a larger system. You would take RISC-V and use it drive your novel VLIW processor.
How? RISC-V will have to have memory model, for example, which will define some at least effective execution model. If you turn RISC-V into not RISC-V you might as well just start from scratch.
