However newer incoming 5-level page intel chips [1] will allow up to 57 bits of address space, 128 PiB in theory though in practice 32 PiB of userland memory. See also [0] for discussion on practical limit for 5-page too!
[0]:https://github.com/lorenzo-stoakes/linux-mm-notes/blob/maste...
Having said that I did write a patch to ensure that the system would boot correctly with 256 TiB of RAM [0] so perhaps I am not always a realist... or dream of the day I can own that system ;)
[0]:https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-n...
This is actually kind of a cute way of dividing kernel and userland space as you just set the upper bit to 1 for kernel addresses and 0 for userland.
EDIT: Specifically talking about x86-64 here.
https://github.com/lorenzo-stoakes/linux-mm-notes/blob/maste...
Apple uses the high bits to cryptographicly sign the pointer value.
It's a useful optimisation technique where you can add some extra metadata without having to dereference a pointer.
As for storing tags in pointers on 64b platforms it is probably better to use the 3 low order bits. Another useful trick is what was used in PDP-10 MacLisp and is used by BDW GC: encode the type information in virtual memory layout itself.
