It should fit, as you said, but the last time I tried it the VHDL front-end for Yosys was not up to it. That might have changed as it was a few years ago.
It is (I think) much better now - it is ghdl as a plugin synthesising to yosys IR. The nightlies from https://github.com/YosysHQ/fpga-toolchain have it all ready to go.
