undefined | Better HN

0 pointsBenjiWiebe4y ago0 comments

SPI isn't addressable.

0 comments

In my experience has been that there exist essentially 2 types of SPI, one addressable by CS, the other (more i2c-like) by the first byte (CS still required to frame the transactions.

I'm working with one of the latter type at the moment that's even worse, it daisy chains chips with each editing the address as it passes through until it hits one where it's 0, they share a CS and a wired-or interrupt, but avoid the need to have 32 CS pins

SV_BubbleTime4y ago

I’ve never seen SPI that doesn’t require a CS line. The whole way that daisy chaining works is this. Do you have a device off hand that uses addressable SPI, I want to see how they explain it in a datasheet.

Taniwha4y ago

I'm afraid the two I can think of have non-publicly available data sheets: one is a cablecrypto device, the other a SLIC. The SLIC is the one with the daisy chain - they want to be able to build phone systems with a SLIC for every slot in a T1 frame - so 24 SLICs - they're trying to avoid 24 CS pins and 24 interrupts on the attached signalling CPU

dfox4y ago

There are some Microchip chips that implement weird SPI/I2C hybrid which does I2C-like slave addressing over SPI. But thats it for the addressing.

emptycan4y ago

Yes it is - that's what /SS is for.

MisterTea4y ago

Chip selects are optional. You can daily chain multiple spi devices and push the data out in a contiguous block. All the chip selects are tied together and only one cs line is used from the cpu.

duskwuff4y ago

> You can daily chain multiple spi devices

For some simple SPI devices, sometimes. Many SPI devices, especially more complex ones, won't let you shift data through the device without attempting to interpret it.

1 more reply

flyingcircus34y ago

Flash memory devices use the CS line as an integral part of the protocol. It is definitely not optional.

jstanley4y ago

If that counts then you can do exactly the same thing with a UART-based protocol, no?

monocasa4y ago

Do you know of any uart hardware that'll only latch on /SS active?

1 more reply

j / k navigate · click thread line to collapse

0 comments

Taniwha4y ago

In my experience has been that there exist essentially 2 types of SPI, one addressable by CS, the other (more i2c-like) by the first byte (CS still required to frame the transactions.

SV_BubbleTime4y ago

Taniwha4y ago

dfox4y ago

There are some Microchip chips that implement weird SPI/I2C hybrid which does I2C-like slave addressing over SPI. But thats it for the addressing.

emptycan4y ago

Yes it is - that's what /SS is for.

MisterTea4y ago

Chip selects are optional. You can daily chain multiple spi devices and push the data out in a contiguous block. All the chip selects are tied together and only one cs line is used from the cpu.

duskwuff4y ago

> You can daily chain multiple spi devices

For some simple SPI devices, sometimes. Many SPI devices, especially more complex ones, won't let you shift data through the device without attempting to interpret it.

1 more reply

flyingcircus34y ago

Flash memory devices use the CS line as an integral part of the protocol. It is definitely not optional.

jstanley4y ago

If that counts then you can do exactly the same thing with a UART-based protocol, no?

monocasa4y ago

Do you know of any uart hardware that'll only latch on /SS active?

1 more reply

j / k navigate · click thread line to collapse