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0 pointsFullyFunctional4y ago0 comments

It's meaningless to look at the code in absence an implementation and conclude anything about the performance. He doesn't know what the performance is. Having six instruction vs. two does not mean one is 3X faster than the other. It means nothing at all.

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stephencanon4y ago

We know enough about the implementation of current RISC-V cores to conclude that they won't be remotely competitive on this one narrow (yet fairly high-impact for some workloads) task. Is it _possible_ to design a core that is competitive on this workload even when handicapped by a limited ISA? Yes, definitely. Have any RISC-V designers shown any interest in doing so yet? No.

j / k navigate · click thread line to collapse

0 pointsFullyFunctional4y ago0 comments

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stephencanon4y ago

j / k navigate · click thread line to collapse