I was also able to find a high resolution picture of the spacewire interface card with its glorious space grade asic packages [2]
Sadly the SSR is not shown, I assume that it is basically a gigantic sheet of sram and a fpga.
[1] https://www.researchgate.net/publication/233962152_Status_of...
[2] https://www.nasa.gov/vision/universe/watchtheskies/jwst_spac...
The concepts of "low power" and "high speed" has changed a lot since JWST was designed.
Say, a low-power, high-speed interface which is USB 3.2 only works via good copper cables and at distances of a few meters.
Now of course it still looks better than most commercial PCBs and far ahead of anything I ever made. But I was expecting a board flying to space to be "perfect", touched up by a gray haired wizard.
How come? Is this actually plenty good, do they cover this in so much conformal coating there is no chance of joint breaking due to vibration and thermal cycling, or what?
Btw the large square packages in the first picture look amazing.
This works out to 2 MB/s.
I'm guessing that could be one of the limiting hardware elements. There must be some redundancy in that right?
68-GB solid-state drive [...] by the end of JWST’s 10-year mission life, they expect to be down to about 60 GB because of deep-space radiation and wear and tear.
https://news.ycombinator.com/item?id=32067945
https://spectrum.ieee.org/james-webb-telescope-communication...
I imagine the contracts could be FOIAed here and specs like anticipated write capacity obtained, would be very interesting to learn about radiation hardening and redundancy for SSDs - err, solid state recorders - in space.
[1] https://www.electronicsweekly.com/news/business/information-... [2] https://www.seakr.com/our-technology/#products
I suspected something like that. I assumed there was a reason there was "only" 65GB of storage up there, when I can get a half terabyte microSD card for under $70 on PrimeDay. Lots of Moore's Law has happened in the last 10 years...
As a RaspberryPi enthusiast, I'm under no illusions about the reliability of microSD cards, but I wonder whether if they were building that data recorder today, that a huge raid 1 with perhaps 20 or 50 mirrors stored on 512GB SD cards might be able to compete on reliability and cost (including launch weight)?
Looks like any other SSD from a few years ago, just bigger and in a metal box.
> The GEN3 FMC is a 192 GByte card designed for space applications. It is a standard 6U cPCI form factor composed of 3 cards: the main controller card and two memory mezzanine cards. It supports data and control transfers via the backplane cPCI bus.
Total noob question but how exactly does this part work? It seems like if you record close to the 4h transmission limit of data between contacts it wouldn't be possible to catch up on next contacts and not fill up the recorder. Is it not possible to record that much data in the timeframe between contacts, or is there some safety margin in the transmission limit they state for this reason?
It's possible they don't "catch up" for a while, getting a few extra bits and pieces over the next several contacts, not just at the contact following that missed.
If you mean the APT (Astronomer's Proposal Tool) this tool was originally developed for Hubble Space Telescope proposals, and has been in use since at least least 2008[0]. A year or two ago, I found that parts of it are written in Common Lisp[1].
[0] https://www.stsci.edu/scientific-community/software/astronom...
[1] https://apst.stsci.edu/apt/documents/documentation/apt-proje...
https://github.com/spacetelescope
The Physical Optics Propagation in PYthon (Poppy) has some neat pictures: https://poppy-optics.readthedocs.io/en/latest/
The Cycle 1 documentation, including the now-expired Call for Proposals is here: https://jwst-docs.stsci.edu/jwst-opportunities-and-policies
