But even reading the original article, it barely mentions Apple and CharlesW highly editorialized that submissions title:
The Apple bit:
> For example, Apple’s A15 has more than a dozen Arm-based CPU cores distributed across the die for various non-user-facing functions. SemiAnalysis can confirm that these cores are actively being converted to RISC-V in future generations of hardware.
The original title:
> SiFive Powers Google TPU, NASA, Tenstorrent, Renesas, Microchip, And More
The bulk of the article is about Google and hyping Risk-V, not Apple.
[0] https://semianalysis.substack.com/p/sifive-powers-google-tpu...
Apple is in a unique position where they have all these Cortex cores for various reasons, but also have the resources to actually design a RISC-V implementation that could replace them all. I doubt the people designing flash controller ICs have that level of design experience.
The big advantage to rolling your own private ISA is that there's already a rich compiler and O/S ecosystem for RISC-V while if you do use RISC-V it's all already there for you.
It really does feel like a second generation 'barn raising'
Designing them is an option. RISC-V's license allows doing so. But, unlike ARM, where your only alternative is to license ARM's own designs, in RISC-V there are several options.
You could use open source cores, or license cores from someone. As there's an open market of cores, there are several competing companies, offering several competing cores and support arrangements.
They already have a their own custom low-power arm64 core design for running these firmware tasks. They have about a dozen of them scattered around the M1, on top of the massive P and E cores.
There are still a few actual ARM inc designed cores spread around the motherboard, in various devices. But inside the SoC, most (if not all) are Apple's own design.
That's the real difference: RV is a real market with multiple vendors whereas ARM arch is more or less single vendor lock-in.
They said "We estimate there are 10bn cores on the market already" (that would be since 2010). Then there's a slide that says "Nearly 80 billion RISC-V CPU cores by 2025".
https://www.eenewseurope.com/en/europe-steps-up-as-risc-v-sh...
that's from a talk at Embedded World in june 2022.
I can't find that talk on youtube. But there's another shorter talk that's online, from same CEO at the same conference, where they have a slide that says "North America. Industry adoption has taken off with millions of cores shipping from Nvidia, Western Digital, SiFive, and others."
...and USB flash drives are more likely to be based on 8051s than ARM in volume.
The company that owns MIPS, Imagination Technologies, has entirely dropped the MIPS ISA to instead focus in designing RISC-V cores.
[1] https://www.techgoing.com/jim-keller-innovation-is-happening...
edit: they still have them.
https://jobs.apple.com/en-us/details/200349341/system-archit...
See also today: https://twitter.com/SiFive/status/1570880204804849671
A lot of the RISC-V action is going on in China which is obviously rather more difficult. Over there much of that is funded by the Chinese state.
Notably, Apple was among main investors when ARM was a startup; they're not doing this to save in ARM fees.
Depending on what you're doing this may or may not be an advantage, but it's certainly a large difference from Arm. It could lead to innovation happening more quickly since there's no need to wait for a gatekeeper, it's unclear at the moment how much that matters.
Given any ARM core (save the wildly inefficient, but faster top performance cores like the X1/X2), SiFive's got one that's like below a third of the size, uses dramatically less power and runs somewhat faster.
This is enabled by the quality of RISC-V's architecture.
The base spec has less than 50 instructions. Even with everything and the kitchensink in there (which is possible; as of the batch of extensions approved in late 2021, RISC-V is not lacking any major features ARMv9 or AMD64 have), RISC-V is still a few hundred instructions, rather than thousands.
And, despite having highly competitive 32bit code density (might be the best by year end, considering with current state of non-finished Zc/B extensions it already is) and the highest code density of 64bit architectures (by comfortable margin), RISC-V is very easy to decode. The compressed code extension does barely even complicate decode, and is still either 2x 16bit instructions or a 32bit one.
In practice, this means cores can be tiny relative to equivalent ARM cores, and SiFive's portfolio is a good demonstration of that.
By contrast:
- AMD64 aka x86 has 1-16 byte instruction length which means a 2-decode or wider implementation has to bruteforce every possible instruction start and discard the bad results. This makes complexity scale exponentially with decode width, and Intel and AMD have found that 4-decode is a practical limit.
- ARMv9's aarch64 is fixed 32bit (yet only slightly easier to decode because of that, relative to thumb2 and RISC-V). This enabled Apple to go 8-decode with the M1. But this comes at the expense of code density: If you want to implement a high performance core, you're going to need a huge L1, which besides huge area and power penalty, is also going to cap the clock the cache can achieve. Regardless, the situation is much better than AMD64(x86), and has enabled Apple to go 8-decode on the M1.
And this is why I think Apple moving to RISC-V in supporting cores is only the first step, and the main cores will eventually follow.
smaller easier to read specs
easier to get new features ratified, org is a steward, isn't seeking rents
easy to add custom instructions
lots of OSH implementations to choose from
large 3rd party ecosystem, IP, compilers, OS, etc.
Don't get me wrong - it's a big deal to have this popular open ISA. But I just don't think it's anywhere near as big a deal as Linux is/was.
Apple ISA. Might take them a decade, but in the end, they will eventually do all their own thing.
*Badumph*
