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0 pointszu2_3y ago0 comments

No. VisionFive2's RISC-V CPU does not have the B extension. I confirmed it on the actual device.

$ cat /proc/cpuinfo processor : 0 hart : 2 isa : rv64imafdc mmu : sv39 uarch : sifive,u74-mc

0 comments

snvzz3y ago

As you say this, I realize I can't find anywhere that it does.

I do not know why I thought it did. Possibly as U74-MC[0] supports that option.

Interestingly, I also took a look at RVA22[1], and found it requires Zbb but not the whole B.

Your /proc/cpuinfo isn't listing Z* extensions. Maybe lscpu output would be more detailed?

zu2_OP3y ago

Oh, I was mistaken. I've verified that at least the rev instruction works (tested on clang -march=rv64imafdcb0p94).

snvzz3y ago

It is quite possible it implements some B instructions (like the Za or Zb extensions) but not B as a whole.

snvzz3y ago

Got mine.

OpenSBI says:

Boot HART Base ISA : rv64imafdcbx

j / k navigate · click thread line to collapse

snvzz3y ago

As you say this, I realize I can't find anywhere that it does.

I do not know why I thought it did. Possibly as U74-MC[0] supports that option.

Interestingly, I also took a look at RVA22[1], and found it requires Zbb but not the whole B.

Your /proc/cpuinfo isn't listing Z* extensions. Maybe lscpu output would be more detailed?

zu2_OP3y ago

Oh, I was mistaken. I've verified that at least the rev instruction works (tested on clang -march=rv64imafdcb0p94).

snvzz3y ago

It is quite possible it implements some B instructions (like the Za or Zb extensions) but not B as a whole.

snvzz3y ago

Got mine.

OpenSBI says:

Boot HART Base ISA : rv64imafdcbx

j / k navigate · click thread line to collapse