Not really less latency so much as the signalling can be run at much higher speed and/or much lower power without having to worry about stuff like the optional termination, the electrical properties of the socket->dimm connection itself, and much shorter track lengths. It also allows you to have as wide a bus as you want, limited by cost of packaging and die sizes on the package, instead of dimm size and board layout, which naturally has a much higher trace pitch than the package.

The higher speed "may" cause lower latency, but it's likely secondary at best.

Memory latency on the M1/M2 is no better than other systems. Other things are better, but not that.

That should happen in the future, but so far Apple hasn't really taken advantage of the massive improvement in signal integrity and their latency is similar to desktop x86. If someone figures out how to overclock one of these machines, we can find out if they're just being extremely conservative or if the memory controller is extremely weak compared to what you see on x86 desktop CPUs.