I meant the memory controller on the CPU side won't need to implement it. Obviously, full DDR5-ECC hardware exists, but the onchip ECC as a whole makes bit flips far less likely than DDR4. There's not much of a need for the complete set on consumer hardware.

Of course this is assuming random cosmic ray bit flips, not faulty hardware. And it's speaking cost-wise from the manufacturer's perspective. I'd personally like full ECC to just be the standard.