It seems unlikely that Power completely lacked atomics. This is a very vague recollection since it's been a long time, but I feel like there were some differences. I think PowerPC used a load-linked/store-conditional with a stronger guarantee than a CAS (compare and swap) on x86. For example, if x = 1 and you CAS it to a new value, another thread might have changed it to 8 and then back to 1 in the meantime and it'll still succeed (the ABA problem: https://en.wikipedia.org/wiki/ABA_problem).

I think x86 also has a stronger memory model providing less flexibility, but greater consistency.

PowerPC uses LL/SC for synchronisation, which is very different to the classic x86 approach. Maybe you didn't like that? But i think Alpha and ARM use that too.

> Perhaps it didn't have atomics at that point? That would've killed it for that project.

That would have been PPC 601 and perhaps [entry level] 603 models. Motorola/IBM first released a single processor PPC, then they added support for multiprocessor systems which did have atomics – https://devblogs.microsoft.com/oldnewthing/20180814-00/?p=99...

Other than that, I immensely enjoyed hand writing PPC assembly – it is a very straightforward RISC design, the «rlwinm» / «rlwimi» instructions are fun – once you figure out how to use them.