RISC-V has a standardised (optional) TSO memory model mode, plus "fence.tso" instruction that works in normal mode, even on CPUs that predate it (it defaults to the stronger "fence rw,rw" in that case). Well, assuming the CPU core designer read the spec carefully and doesn't trap on unknown "fence" instructions (looking at you, THead...)

I was speaking to whether the code will work. The answer is almost always yes. Optimizations at a higher level such as algorithm choice or where allocations are performed also are architecture neutral. This is most optimization.