That is a very simplistic look at it. We don’t know if TSMC has already done a lot of testing and thinks it can do it.
Meanwhile, Intel absolutely needed to try to take much bigger risks.
A pretty good article showing that low NA might be more cost effective: https://www.semianalysis.com/p/asml-dilemma-high-na-euv-is-w...
Lastly, the biggest chip you can make with low NA is 858 mm² which is nearly 2x bigger than high NA at 429 mm². This means it's impossible to make a chip as large as the Nvidia H100 GPU using high NA. If Nvidia uses Intel's 14A process, they will have to split the chip into multiple pieces and go chiplets approach. They're already doing it with Blackwell but that's stitching 2x 800mm²+ dies together. If they make a future chip using high NA nodes, they'd have to stitch 4x dies together to have the equivalent size which is considerably harder for GPUs.
I do believe that all highend chip makers will be switching to the chiplet approach. Everyone has to due to the high NA reticle limit. But TSMC's approach allows designers to keep making chips twice the size until around 2030. That's a huge advantage.
