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0 pointsduskwuff1y ago0 comments

> It just seems so obvious today that you can create gates, you can create macros, you can create complex designs, and you can define the interface at every level so you can hook them up and they just work. That idea came out of Conway and the early pioneers of VLSI.

And you can see the opposite of this in many early microprocessor designs, like the (original, NMOS) 6502 and Z80. There's a lot of highly idiosyncratic designs for gates, heavily customized for the physical and electrical context that they're used in - and I won't deny that they're often very clever and space-efficient, but they were also extraordinarily time-intensive to design, and weren't reusable. It made some complex designs possible within the limitations of the time's fabrication technology, but it wasn't an approach which would have ever scaled to larger designs.

One great example of this is this bit of 6502 overflow logic:

http://www.righto.com/2013/01/a-small-part-of-6502-chip-expl...

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jefftk1y ago

> There's a lot of highly idiosyncratic designs for gates, heavily customized for the physical and electrical context that they're used in - and I won't deny that they're often very clever and space-efficient, but they were also extraordinarily time-intensive to design, and weren't reusable.

Is this optimization now something that hardware design tools do automatically?

duskwuffOP1y ago

They optimize on a different level. Instead of trying to optimize the arrangement of individual transistors, you start with a set of standard cells which contain optimized transistor-level implementations of individual gates, and have your design tools optimize the placement and routing of those cells within a grid system.

jefftk1y ago

Does that mean there's an opportunity for increasing performance by bringing collections of gates into scope for optimization? Or does that not actually let you decrease transistors very much?

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0 pointsduskwuff1y ago0 comments

One great example of this is this bit of 6502 overflow logic:

http://www.righto.com/2013/01/a-small-part-of-6502-chip-expl...

0 comments

jefftk1y ago

Is this optimization now something that hardware design tools do automatically?

duskwuffOP1y ago

jefftk1y ago

Does that mean there's an opportunity for increasing performance by bringing collections of gates into scope for optimization? Or does that not actually let you decrease transistors very much?

2 more replies

j / k navigate · click thread line to collapse