OpenTitan (RISC-V based tamper-resistant open specification RoT/TPM/SE) themselves have a neat write-up on designing against hardware attacks: https://opentitan.org/book/doc/security/implementation_guide... / mirror: https://archive.vn/UqAVo
I came across Satnam Singh's work first while learning about the Lava language/framework for FPGAs, glad to discover his more recent work.
Does anyone know which kind of the two above this course is? I couldn't find that info.
Does it reflect university teachers getting younger? Or younger teachers tend to give more effort to putting everything online? Or did my perception change with age?
Hopefully someone out there finds it useful!
Good times!
Our labs include building your own real spectre attack against the kernel, bypassing ASLR and building ROP chains with various side channels, finding and exploiting backdoors in a RISC-V CPU by building a hardware fuzzer, and more.
(source: I designed the Spectre lab plus a few others)
All our labs are fully open source for anyone to try: https://github.com/MATCHA-MIT/SHD-StarterCode
If you give them a try, please do let us know what you think! We genuinely want these activities to be fun and approachable (we designed them like a big CTF) and welcome feedback from the community.
