Just like old C64 decrunchers and Amiga PowerPacker. Or Fabrice Bellard's LZEXE. (Is there anything that guy did NOT write?!)
This is great for making audio modules, where the firmware is be small and operates on a big audio buffer. Since the biggest available PSRAM chips are 8MB, this combined 16 MB could hold around 3 minutes of mono 16-bit audio, which allows for a very nice multi track looper.
Another way (in case there's no other MCU to help with uart bootstrap) would be to add a logic chip to multiplex the CS line between Flash and the first PSRAM - copy firmware to flash and then switch to using ram.
Rather than UART booting every time I thought it might be nice to use UART Boot just as a way to deliver the firmware update to the sub chip - so the UART image you load would just be a program that accepts a larger image (over UART again) and would write to the flash for subsequent boots. I think that would get around the SRAM and boot time downsides the author mentioned. Is there a reason this might not work?
https://github.com/pimoroni/picovision/blob/main/drivers/dv_...
SWD is pretty well documented. I won't claim its simple, but, in my opinion, it's decent at what it does. The RISC-V folks haven't seemed to be able to do better (and, IMO, did quite a bit worse in a few places, actually).
The SWD description at the packet/command level: https://arm-software.github.io/CMSIS-DAP/latest/index.html
There is open source code directly from ARM for it: https://github.com/ARMmbed/DAPLink/tree/main/source/daplink/...
The documentation of the actual wire protocol is also extensive, but a little more scattered: https://developer.arm.com/documentation/ihi0031/a?lang=en https://community.nxp.com/pwmxy87654/attachments/pwmxy87654/...
The big problem with the SWD wire protocol ARM documentation (and everybody who copies it) is that they don't point out the fact that when you go from Write-to-Read the active edge of the clock changes. In SPI-speak, you switch from CPHA=1 to CPHA=0. This makes sense if you stop to think about it for a moment because during debug there is no clock. Consequently, SWD must provide the clock and you switch from "put something on DATA a half phase early->pulse clock to make chip do something with it" to "pulse clock which makes chip put something on Data->read it a half phase later". However, if it has never been pointed out to you before, it's likely to trip you up.
Sigrok (or similar) which can decode SWD properly and a digital signal analyzer (even a cheap $10 one) are your friends.
The only diagrams which seem to resemble scope traces that point this out are on obscure Chinese engineering blogs.
Thanks for the writeup.
Later, Espressif took that chip, modified bootrom to be able to boot from an SPI flash as well, and marketed that variant as "ESP8266". Serial bootloader was kept as a debug/programming interface, and that was inherited to ESP32 and later chips. All of which can boot directly from serial.
