Distance-Based ISA for Efficient Register Management (opens in new tab)

When I read these papers I always wonder if the authors did any research into priors before doing their work. I usually see sus-af "redos" in low tier AI (the fad of the decade); so, CPU arch is original? Another commenter pointed out Mill is probably the closest one I can think of off the top of my head. I think the old rolling window Power stuff IBM published in the ... 90s? might be exactly this? I can't remember if that arch used an autowindow (STRAIGHT) or if it was more manual.

EDIT: Derp! RIP-relative x64? I've not coded x64 in 15 years, so I don't remember how pervasive the addressing mode is.

I guess the author's are trying to explore a ground-up implementation? Maybe the uarch is really exotic?

They say that "the distance-based representation is novel", but it seems at least similar to the Mill CPU's belt idea.

The article mentions getting SPEC CPU running but doesn't share performance results or scalability results (now the CPU can decode twice as many instructions, etc). Can someone who has been following the research in this area share some results?

A question, is it distance as in from the PC (absolute addressing from a datum) or as in the number of instructions executed (meaning a 4 byte conditional branch can shift the whole history)?