One of the things I would absolutely love to have are a couple of FPGAs boards in SFP and QSFP form factors. Why might you ask? Because it would be seriously useful to have a PPPoE / L2TP data plane to plug into the port of a 100Gbps capable switch for use in the network edge. Modern ethernet switches have plenty of Layer 3 networking capabilities, but most switch vendors fail to expose any functionality for these protocols even though the underlying ASICs often enough have the capability to handle them. Sure, you'll never see these protocols in a cloud data center, but plenty of incumbent telecoms make use of them in their FTTP networks due to the legacy of xDSL deployments and the need to support wholesale access to those networks. Sadly, developing such a board is beyond my hobbyist electronics capabilities, but I'd have no problem bashing a bunch of Verilog / VHDL into shape to make it work in fairly short order... I just hope it uses an FPGA like the Polarfire for which the SERDES are about 100x easier to use than the gawd awful Xilinx 7 series (KC705, I'm glaring at you for eating weeks of my hobbyist life to that bring up).
Microchip has an app note on putting a Polarfire into an SFP+ module complete with a board layout, but nobody is building them as near as I can tell. Lattice has a similar app note, but, again, they only sell the much larger eval boards.
As many of you probably know, SERDES and specialized PCS/CDR blocks will get you well past 1 GigE, but 1 GigE for RGMII is challenging with 125 MHz single-ended traces.
The project compiles super fast with the Quartus tools and Signal Tap enabled with several active configurations. Quartus bundles the Questa simulator, so there is a great environment for simulation.
Regarding Certus-NX, this indeed would also be a great choice. Lattice does a very nice job exposing their I/O primitives, and I believe the RGMII DDR could be instantiated directly in the I/O cells for both input and output (this could definitely be accomplished with the earlier ECP5). We actively design with Certus-NX, and a future Betsy revision using it is very possible.
1) As others mentioned, two GbE interfaces seems really limited for a 2025 project. Modern FPGAs can support 100GbE and up - I don't necessarily expect that on a hobbyist-level project, of course, but 1GbE is well behind the curve.
2) There don't appear to be any hardware design files (e.g. schematics, PCB layouts) in the Git repository. In fact, the only mention of the current FPGA is a single text file stating that "Cyclone 10 GX port in progress"...
3) There's basically zero open source support for Intel/Altera FPGAs. Yes, you can open-source your HDL, but the vendor tools are all closed-source and there's no alternatives.
If the restriction is wanting low price to suite the FPGAs open-source low-budget market, they'd be better off using a Lattice Certus-NX or something. 5Gbps SERDES on that for ~$40, or better yet a CertusPro-NX with 10Gbps SERDES for ~$70. Altera and Xilinx are just throwing away the sub-100K-LUT market to Lattice at this point, yet people are still building systems out using these expensive, antiquated parts. That's shelf pricing too - go through a distributor and it'd be 50% of that price!
