Adding to what was said, it also suspiciously looks like a MIPS core with a RISC-V frontend strapped to it sort of like Qualcomm did with their Nuvia AArch64 core. Particularly stuff like the soft fill TLB from m-mode looks just like MIPS coprocessor 0.

I can only refer to MIPS' own press releases, unfortunately. They mention 4-wide OoO, RV64GH + Zbb + Zba. no V.

That is a frustrating pattern in the RISC-V world. Many companies that boast having x wide cores with y SPECint numbers but nothing that has been independently verified.