Maybe RISC-V? It's right there in the name, but I haven't really looked at it. However, there are no RISC-V chips that have anywhere near the performance x86 or ARM has, so it remains to be seen if RISC-V can be competitive with x86 or ARM for these types of things.
RISC is one of those things that sounds nice and elegant in principle, but works out rather less well in practice.
RISC-V is specified as a RISC (and allows very space-/power-efficient lower-end designs with the classic RISC design), but designed with macro-op fusion in mind, which gets you closer to a CISC decoder and EUs.
It's a nice place to be in tooling-wise, but it seems too early to say definitively what extensions will need to be added to get 12900K/9950X/M4 -tier performance-per-core.
In either case though, a bunch of the tricks that make modern CPUs fast are ISA-independent; stuff like branch prediction or [0] don't depend on the ISA, and can "work around" needing more instructions to do certain tasks, for one side or the other.
A RISC architecture was actually one with simple control flow and a CISC architecture was one with complex control flow, usually with microcode. This distinction isn't applicable to CPUs past the year 1996 or so, because it doesn't make sense to speak of a CPU having global control flow.
https://www.extremetech.com/extreme/188396-the-final-isa-sho...
The CISC decoder is like a "decompressor" that saves memory bandwidth and cache usage.
