Designing a Low Latency 10G Ethernet Core (2023) (opens in new tab)

You can code a failsafe, or what they call in other industries, an interlock. If an order exceeds some sane limit, or a loss is incurred that exceeds a limit, or the limit-checker fails to proactively ping the interlock, then an independent mechanism shuts it down.

This is how, say, a modern x-ray machine prevents itself from failing in a way that radiation gets stuck on.

The way to think is the opposite: your system is making millions per hour.

On the other hand, no nights or weekends.

I'd want to know why they had such a system as a single point of failure

It's a bit unfair to call it pointless. Empirical studies have shown that HFT increase liquidity in markets, leading to narrowed spreads, market depth, faster execution speeds, cross-market informational efficiency, etc. All of these are generally beneficial to other non-HFT market participants.

Now you might counter that it also brings some negatives (e.g. fleeting liquidity, market manipulation risk, etc.) and there's certainty some validity to that. But none of this supports an argument that it's pointless.

More generally, activities aren't pointless if you are earning money from it which pays your rent, puts food on your table, etc. A large portion of the world works mainly for this goal. It's perfectly valid to tell your grandchildren "I spent my life making sure we'd have enough money for you and your parents to live comfortably", and we shouldn't look down on someone who does that.

High frequency trading is far from the only pointless activity software and hardware developers are employed to do. At least in that realm they are pushing the state of the art, unlike presenting ads or yet another crud app.

Will the grandchildren be able to hear you over the roar of the yacht?

Meh, at least HFT is making sure markets are efficient.

Now imagine telling your grandkids you worked on pushing short form content in absolutely every app to maximize engagement and rot brains?

“You’re welcome for the education and good home full of books.”

Are L1 switches like hubs or repeaters then? Sorry for my confusion.

In fairness, assuming 4/8 ports in, 4 ports out, operating at some ungodly GHz using a custom GaAs or SiGe chip, and working in gearboxed scrambled space with very clever input mac prefix mapping and output scrambled/gearboxed precomputation, one _could_ do around 8ns optimistically from the start of the first 64b/66b block (the 0x55... preamble) for 10GB. There's some stuff about preamble shrink that makes it wonky, but that is doable. And interestingly enough, for 25G-R, one can comfortably do this in about 4ns. I am not in fact aware of such a beastie existing for 25G, but I have seen 1 or 2 for 10G though.

Surprisingly, if ChatGPT is prompted _juust_ right, it will even give you a good way to do this.

This guy knows a thing or two about these devices ;)

You can go quicker with CXL, but not by much.

why do you assume the full ethernet header?

IIRC. cut-through only needs the first 6 bytes. Since it only needs the destination address for the port lookup.

Potentially the first bit, on broadcast.

Not my are of expertise, but afaik the neat part is that you don't do it in cycles. The "program" lives as the transistor layout, not as instructions

I’m not the parent, but I’d assume that this was an impressed ‘yikes.’ While Jane is not the most well known firm for ultra low latency trading, an FPGA engineer from that firm could be considered an expert practitioner in the field.

Some people just love dropping “yikes” type comments and then never explaining themselves.