The flourinert tank has a ball valve, like a toilet cistern. we hung a plastic lobster in ours, because we called the cray "Yabbie" (Queensland freshwater crayfish)
That re-generator, the circuit breakers are .. touchy. the installation engineer nearly wet his trousers flipping on, the spark-bang was immense. Brown trouser moment.
The front end access was Unisys X11 Unix terminals. They were built like a brick shithouse (to use the australianism) but were a nice machine. I did the acceptance testing, it included running up X11 and compiling and running the largest Conways game of life design I could find on the net. Seemed to run well.
We got the machine as a tax-offset for a large Boeing purchase by Australian defence. End of life, one of the operators got the love-seat and turned it into a wardrobe in his bedroom.
Another, more boring cray got installed at department of primary industries (Qld government) to do crops and weather modelling. The post cray-1 stuff was .. more ordinary. Circular compute unit was a moment in time.
(I think I've posted most of this to HN before)
Another rationale may have been that the flywheel on the motor-generator would cover a multitude of power-quality sins.
Aerospace originally did that to reduce component size, CDC and IBM took advantage of the standard in the early 60's.
Strangely, it seems mainframes didn't adopt switching power supplies until the end of the 70's, despite the tech being around since the end of the 60's.
It wouldn't surprise me if we had the bastard love-child of leftovers from Boeing.
Just before a tour group came by, he hid inside the Cray, and waited for them to arrive. Then he casually strolled out from the back of the Cray, pulling up the zipper of his jeans, with a sheepish relieved expression on his face, looked up and saw the tour group, acted startled, then scurried away.
Getting access took just short an act of God and I was a sysadmin in the central support group! They didn't want us puttering on the machines, so as far as I could tell it mostly sat idle.
Unsurprisingly, I would say, the Cray is literally the prime example in "A Gallery of Computers as Furniture".[†]
And, yes, quite some time ago I noticed that my cell phone had surpassed the capabilities of these early Crays :)
That’s 20 years or about 10,000X the available VLSI transistors via Moore’s Law.
Sometimes I like to remind myself we are living in the future. A future that seemed like SciFi when I was a kid in the 70s!
Sadly I don’t think we will ever see Warp Drives, Time Travel or World Peace. But we might get Jet Packs!
"The 160 MFLOPS Cray-1 was succeeded in 1982 by the 800 MFLOPS Cray X-MP, the first Cray multi-processing computer. In 1985, the very advanced Cray-2, capable of 1.9 GFLOPS peak performance
...
By comparison, the processor in a typical 2013 smart device, such as a Google Nexus 10 or HTC One, performs at roughly 1 GFLOPS,[6] while the A13 processor in a 2019 iPhone 11 performs at 154.9 GFLOPS,[7] a mark supercomputers succeeding the Cray-1 would not reach until 1994."
Sadly most of that power is not working for you, most of the time, but working against you, by spying, tracking and manipulating you.
Bet that was not include in your sci-fi dreams in 70s..
You'd need a different comparison to show how the Cray-1 was special. If the comparison is to single commodity CPUs, like the Pentium MMX, you could make much the same comparison for many mainframes and supercomputers. Several supercomputers in the 1980s exceeded 1 GFLOP, for example, and it wasn't until the 2000s that you could get commodity CPUs with that performance.
The Transputer's inter-chip channel connections remind a bit of Nvidia's NVLink or AMD's Infinity Fabric.
I was working at a geophysical company in the 80's and we lusted after a Cray-1. Best we could afford where array processors (CSPI) connected to VAX systems.
i don't think there is a comparable book about the cray-1?
Blitz was ported to C and continued development FOSS as Crafty, mainly by a U of Alabama professor, but to this day it can't beat top humans on modern cpu (topping at 2650 elo instead of 2850 of, say, carlsen.)
I am also of the opinion that with an optimised program the CRAY-1 would have been on par with Karpov and Fischer. I also think that Stockfish or some other strong program running on an original Pentium could be on par with Carlsen. I am not sure if Crafty’s licence would count as FOSS.
Thoughts:
1. To block some sunlight from getting in.
2. It’s a secure facility and wanted to prevent people from looking in.
3. To not have to look at something outside.
4. It’s a secure facility and wanted to prevent the chance of taking a picture of someone or something outside that could compromise the location of the computer or someone’s identity; sometimes the first place a photogenic computer was built was at a customer site.
As for windows in a computer room, seems a bit unusual, but a nicer working environment than the usual windowless box I'd guess...
Remember in 1980 the modern PC wasn't even invented (Apple II was) yes. Most people didn't have access to any terminal as part of their job, only specialized positions did. Typewriters where was everyone had on their desk. As such a computer was something a company could wow visitors with. Times have changed.
"Seymour said he thought it was odd that Apple bought a Cray to design Macs because he was using Macs to design Crays. He sent me his designs for the Cray 3 in MacDraw on a floppy.” reports KentK.
https://cray-history.net/2021/07/16/apple-computer-and-cray-...
(emphasis mine)
In my back pocket. To watch cat videos.
Well... we're there. Far past, in fact. We live in the future that then was so far out of reach that people could only joke about it, not consider it a realistic possibility.
In one lifetime.
Yes, would be nice to compare the capabilities (multiuser, multitasking, security, RCE). Did we get _so_ far ? How many users can a Mac sustain ?
M4 CPU - 280 GFLOPS
M4 GPU - 2900 GFLOPS
I know a couple of museums have them, but I don't think any software has ever surfaced, am I right?
Did I miss it?
The Cray-1 didn't have a hardware stack, so subroutine call is basically just jump there and back, using a register for the return address rather than pushing/popping it to/from the stack.
Another oddity of the instruction set that stands out (since I'm in process of defining a VM ISA for a hobby project) is that the branch instructions test a register (A0 or S0) rather than look at status flags. In a modern CPU a conditional branch, if (x < y), is implemented by compare then branch where the compare instruction sets flags as if it had done a subtraction, but doesn't actually modify the accumulator. In the Cray this is evidentially done by doing an actual subtraction, leaving the result in A0, then branching by looking at the value of A0 (vs looking at flags set by CMP).
Gemini explains this as being to help pipelining.
There's some more detail here: https://ed-thelen.org/comp-hist/CRAY-1-HardRefMan/CRAY-1-HRM...
The following quote gives some sense of how "manual" this was:
> "On execution of the return jump instruction (007), register Boo is set to the next instruction parcel address (P) and a branch to an address specified by ijkm occurs. Upon receiving control, the called routine will conventionally save (Boo) so that the Boo register will be free for the called routine to initiate return jumps of its own. When a called routine wishes to return to its caller, it restores the saved address and executes a 005 instruction. This instruction, which is a branch to (Bjk), causes the address saved in Bjk to be entered into P as the address of the next instruction parcel to be executed."
Details were up to the compiler that produced the machine code.
You have to push it to your preferred stack before the next operation. You do the cycle-counting to decide if it’s a good ISA for your implementation, or not.
Obviously, ISAs with a JSR that pushes to stack are always using an extra ALU cycle for the SP math, then a memory write.
Doing it with a (maybe costless) register transfer followed by (only sometimes) a stack PUSH can work out to the same number of cycles.
With improvements in memory speed or CPU speed, that decision can flip.
Consider that in this era, your ALU also had the job of incrementing the PC during an idle pipeline stage (maybe the instruction decode). Doing a SP increment for a PUSH might compete with that, so separating the two might make the pipeline more uniform. I don’t know any of the Cray ISAs so this is just a guess.
