If I understand the architecture it's both -- a main MPU style core and then a bunch of PicoRiscV cores doing MCU tasks. The smart thing about using RISC-V here being having a unified ISA so you can compile programs that run on both or move between both, etc.
I'm assuming he probably has some sort of roundrobin shared memory access similar to what Chip did with "HUB Ram" on the P2.
