mbell is right -- rather than just adding parasitic capacitance and inductance estimates to every node, it's more helpful for the engineer to be able to evaluate and discover which nodes are particularly sensitive and which aren't. Start with some back-of-the-envelope order-of-magnitude estimates (maybe guess ~1nH/mm inductance for a wire, ~1pF capacitance between adjacent pins), and an experienced engineer will already be able to eyeball likely trouble spots in your circuit. The novice can certainly use the same concepts with simulation to do quite a bit of "debugging" in just a few minutes, for example dragging around a 1pF cap between a bunch of pins, re-running the simulation each time, and seeing where it has the most detrimental effect on an analog circuit.
Just to add, if you want to 'fail safe' a breadboard design, your better off assuming ~25pF of stray capacitance per breadboard insertion point. You should also make sure your circuit bandwidth is less than ~8-10Mhz, keeping in mind that if you have an opamp with GBP of 20Mhz and you're using it with a gain of 2, you may have a problem. Stray inductance can also play a part, but it's far less likely.
