More to the point, Boolean expressions and truth tables are not equivalent representations that should be treated on an equal footing; there's an exponential blowup involved when converting from one to the other. Just try extending that 4-bit adder to 16 or 32 bits. The functions that can be tractably represented using this scheme are a strict (very small) subset of the functions that can be computed by true Boolean circuits.
It is the programmer's job to decide what point on the "using storage"<->"using CPU time" continuum is appropriate for the current problem. Obviously, larger chained adders at 16 or 32-bits would be crazy. (of course, at that point you would want to implement a carry lookahead anyway to avoid the horrible propagation delay in the last carry bit)
Edit: Just to clarify, the disappointment is from being excited that something like this could be wired up the way we initially thought. The result remains cool and clever all the same.
Indeed one can dynamically any kind of rapidly-reconfiguring FPGA-array into a very peculiar and high-performance general parallel processor.
