SiFive Introduces 7 Series RISC-V Cores with E7, S7 and the U7 Series (opens in new tab)

Affordable RISC-V systems will only happen if they reach a comparable level of mass production as proprietary systems. What you will more likely see for now is a gradual increase in the number of components on GPUs, HDDs etc which use RISC-V instead of ARM or something else. The ISA is only a part of the cost equation.

The LowRisc project seems to have the mission you're looking for:

"What are the goals of the project? To create a fully open SoC and low-cost development board and to support the open-source hardware community. This will involve volume silicon manufacture..."

They have 2 folks with prior experience on the Rpi team. But, it's hard to tell when they might have something ready. http://lowrisc.org

They sell an Arduino-class device (technically a computer) called the HiFive1 for $59, and there was a crowdfunded SBC called the HiFive Unleashed that was a limited run for $999. Both are about 5-10x too expensive for poor me, but I'm keeping my hopes up for a commodity-priced SBC to replace my laptop when it finally kicks the bucket.

With QEMU you can already do amazing things. Every component required by Linux From Scratch has been stable, and you can get a Fedora/Debian image for that as well.

Some progress reported a few months back https://news.ycombinator.com/item?id=17642872

There are none yet. RISC-V is likely to appear in embedded and mobile devices before a full desktop machine is competitive with Intel processors.

I'm not sure how useful one of those would really be, to be honest. There's not really much benefit in terms of openness - even though the architecture is open, these actual implementations are entirely proprietary with license agreements that forbid reverse-engineering. Plus it's just not as widely supported as ARM on the software side right now.

I recommend the 6502[1] if you're just starting. What you learn applies almost everywhere, and it's very much a what-you-write-is-what-happens sort of processor. No branch prediction, no caches, no fancy features. Its op-set is very small and highly expressive. They still make them, in fact.

That said, whether you choose to start with it or RISC-V, from personal experience SiFive's implementations are phenomenal. I used one of their free-implementations, and I was blown away by how easy it was to use their automated tools to build a core exactly the way I wanted. Not as easy as generating a NIOS core, but much more capable. With an Artix-7, I had a very capable low-range processor in about an hour.

[1]: https://skilldrick.github.io/easy6502/

The base instruction set is small enough to fit on a card. Of course adding the floating point, vector extensions, etc. would make it a bit harder to squeeze into a single page, but I think it would still end up smaller than the x64 spec.

https://www.cl.cam.ac.uk/teaching/1617/ECAD+Arch/files/docs/...

I'm not sure that's a useful metric; in almost all architectures there's a "core" set which gets used the vast majority of the time in most programs, plus an increasing number of extensions for very specific purposes. You could start today on ARM with the top 20 instructions and get quite a long way.

>But after learning about how small the RISC-V instruction set is (less than 50 apparently, but I can't find a citation for that anywhere), I'm far more motivated to get into it.

from the times when x86 wasn't that big: http://pastraiser.com/cpu/i8080/i8080_opcodes.html

30 years ago we were typing the hex codes of those commands straight into the Forth words bodies using the mental copy of that table (as you see it has very logical easy to remember organization)

The 6809 doesn’t get enough love. It was quite good for the era, easy to learn, and could support things like OS/9.

https://en.wikipedia.org/wiki/OS-9

MIPS isn't bad either. Both are pretty small and well-designed, and not particularly complicated.

Check out MSP430 is you want small instruction sets, also fits on one page if needed.

That shouldn't be super hard. I don't think there is much assembly in either. And C can be compiled to RISC-V already.

My only experience porting node was to a specialized ARM system a while ago, so ARM support may have been already built in or things may have changed.

edit: as people have commented, there indeed is a fair amount of arch specific stuff for reference the mips directory https://github.com/v8/v8/tree/master/src/mips64

M7 is actually an in-order processor. It does have six-stage dual-issue pipeline.

Apparently good Cortex-M7s get around 5 CoreMark/MHz (NXP crossover, STM32H7), so it's almost identical per MHz, and I'm willing to bet that they can get higher frequencies with less effort (if you look at the SiFive MCUs, they run at stupid frequencies compared to similar competing cores, and were generally available almost two years ago now). For further comparison, the Broadwell Xeon I'm typing this on gets about 7.2 CoreMark/MHz (running at full turbo, 4GHz, on one core).

The only place I see that mentions 16 KB is the instruction cache on the S7 monitor core. Apart from cache, it doesn't look like any of these include RAM.